Conventional methods of forming integrated circuit devices may include steps to form single and dual damascene structures using copper (Cu) as an electrical interconnect material. As illustrated by FIGS. 1A-1D, some of these conventional methods may include forming an electrically insulating layer 10 on an underlying integrated circuit substrate (not shown). This electrically insulating layer 10 may be a material having a low dielectric constant, which supports low capacitive coupling between adjacent conductive layers and patterns (not shown). The electrically insulating layer 10 may be a material such as porous SiCOH, which is treated as having an ultra-low dielectric constant (ULK) compared to other conventional insulating layers used in semiconductor processing. The electrically insulating layer 10 may be formed to have a thickness in a range from about 500 Å to about 20,000 Å. Thereafter, a hard mask layer 12 is formed on the electrically insulating layer 10. The hard mask layer 12 may be formed as a SiO2 layer having a thickness in a range from about 50 Å to about 2,000 Å. The electrically insulating layer 10 and the hard mask layer 12 may be treated collectively as an inter-metal dielectric (IMD) layer. A selective etching step is then performed using a mask (not shown) to define a plurality of spaced apart vias 15 extending through the hard mask layer 12 and at least partially through the electrically insulating layer 10, as illustrated by FIG. 1A. A planarization layer 14 is then conformally deposited on the hard mask layer 12 and into the plurality of vias 15. This planarization layer 14 may be an organic planarization layer (OPL) formed of a material such as a hydrocarbon-based polymer, having a thickness in a range from about 500 Å to about 10,000 Å.
Referring now to FIG. 1B, a low temperature oxide (LTO) layer 16 having a thickness in a range from about 100 Å to about 2,000 Å is deposited on the planarization layer 14. An optional anti-reflective coating (ARC) 18 is then deposited on the LTO layer 16. The anti-reflective coating 18 may be formed of a hydrocarbon-based polymer material and may have a thickness in a range from about 100 Å to about 10,000 Å. A layer of photoresist material is then deposited and patterned to define a mask 20 having openings therein that expose the anti-reflective coating 18. Thereafter, as illustrated by FIG. 1C, a reactive ion etching (RIE) step(s) is performed to selectively and sequentially etch through the anti-reflective coating 18, the LTO layer 16, the planarization layer 14, the hard mask layer 12 and the electrically insulating layer 10 to thereby define a plurality of trenches 22a, 22b and 22c within the IMD layer. The mask 20, the anti-reflective coating 18 and the LTO layer 16 are also removed using multiple etching steps. Finally, as illustrated by FIG. 1D, remaining portions of the planarization layer 14a are removed from the hard mask layer 12a and the via holes to expose resulting interconnect trenches 22a′, 22b′ and 22c′, which may be subsequently filled with an electrically conductive material (e.g., copper, not shown). This removal step is performed using an ashing step.
As will be understood by those skilled in the art, the planarization layer 14 operates to compensate for variations in underlying topology differences and thereby widen the process window for subsequent lithography steps. Moreover, the planarization layer 14 is typically formed of a material having relatively good RIE endurance, which enables the planarization layer 14 to operate as a good pattern transfer medium to pass the pattern of the mask 20 to the underlying IMD layer during etching. Unfortunately, in order to reduce ashing damage to the electrically insulating layer 10, a relatively mild ashing process may be required to remove remaining portions of the planarization layer 14a. However, the use of a relatively mild ashing process may result in the formation of planarization layer residues within the vias 15 after the ashing process is completed. Increasing the RIE endurance of the planarization layer 14 in response to decreasing its thickness to reduce RIE bias may also increase the likelihood of formation of planarization layer residues within the vias 15.